Currently, many communication devices manufacturers are incorporating multiple radios into their products. As this trend continues, more and more radios will be integrated into the same communications device and/or onto the same integrated chip or system on a chip (SoC). In order for radios to be integrated onto the same chip, SoC or into the same device, it is critical that they coexist with each other. This is an important issue in the design of multi-radio systems that is only gaining in criticality of operation as the number, complexity and frequency band use of radios increases with time.
As an example, consider the block diagram illustrating an example prior art multi-radio communication system as shown in FIG. 1. This example multi-radio communications system, generally referenced 10, comprises a plurality of radios 12, including various cellular and connectivity specific radios such as Global System for Mobile communications (GSM), Global Positioning System (GPS) (receive only), Frequency Modulation (FM) (receive and possibly transmit), Bluetooth or other Near Field Communications (NFC) and Wireless Local Area Network (WLAN).
Having multiple radios in a single device provides benefits and advantages to users by enabling the operation of several radios simultaneously. For example, a user may be listening to an FM radio station over a Bluetooth headset while using the GPS radio to navigate to a destination and carrying on a conversation over a cellular radio link.
Another aspect of coexistence is the long term trend of implementing as much of the radio in digital as is practical and to integrate as much of the radio as possible into a single chip. With the explosive growth of the cellular phone industry, the need has arisen to reduce cost and power consumption of mobile handsets. To keep costs down, the entire radio, including memory, application processor, digital baseband processor, analog baseband and RF circuits, would ideally be all integrated onto a single silicon die with a minimal count of external components. The use of low-voltage deep submicron CMOS processes allows for an unprecedented degree of scaling and integration in digital circuitry, but complicates implementation of traditional RF circuits. Furthermore, any mask adders for RF/analog circuits are not acceptable from a fabrication cost standpoint.
A consequence of this is the presence of multiple high rate clocks that are needed to drive the massive digital logic circuits. The clocks from one radio can interfere not only with the operation of other radios but with the operation of that radio itself. In particular, in single chip wireless systems (i.e. systems with RF transceivers and digital logic), digital clocks can potentially leak into the RF antenna port or other parts of the system and desensitize the receivers. Due to the very low input power required for good packet (or signal) reception and the relatively high currents drawn by the digital portions of the system, it is usually impossible to provide sufficient on-chip isolation between the digital circuitry and the RF circuit portion. Consider the prior art receiver and transmitter circuit examples presented infra.
A traditional receiver/transmitter (i.e. transceiver) chain clock scheme uses a single root frequency to derive the needed clock signals. All digital blocks use this frequency or an integer division of it as the clock signal which feeds the digital logic. This frequency is typically an integer multiplication of the system symbol rate.
A first example prior art digital receiver (RX) chain clock scheme utilizing a single frequency PLL is shown in FIG. 2. The prior art receiver, generally referenced 20, comprises data path blocks and clock generation blocks. In particular, the data path blocks comprise an analog to digital converter (ADC) 22, decimation filter 24 and digital RX chain (DRX) 26, which comprise the demodulation blocks. The clock generation circuit block comprises single frequency phase locked loop (PLL) circuit 28 (usually locked onto a crystal oscillator) and one or more clock frequency dividers 30.
In operation, the analog signal 31 (RX DATA IN) received from the RF receiver front end module (FEM) is typically an intermediate frequency (IF) or a zero IF (ZIF) signal. This IF signal is input to the ADC 22 and converted to digital samples using a high rate clock 32. This high rate clock is generated in a Phase Locked Loop circuit 28, using a reference clock signal FREF. The output of the ADC is a digital signal 33 sampled at high rate which is then typically down sampled in decimation filter block 24 to generate decimated signal 35. The decimation filter block typically comprises a low pass anti aliasing filter. The down sampled signal 35 is enabled due to the narrowband characteristics of the received signal. The decimated signal 35 is then input to the digital RX block 26, which perform the demodulation functions responsible for extracting the information bits out of the received signal. Note that the entire digital chain is fed with low rate clock signals 34 which are generated by dividing the high rate clock 32 generated by the PLL 28. The high rate clock is divided using the clock divider circuit block 30.
A second example prior art digital receiver (RX) chain clock scheme utilizing a single frequency PLL is shown in FIG. 3. The prior art receiver, generally referenced 40, comprises data path blocks and clock generation blocks. In particular, the data path blocks comprise an analog to digital converter (ADC) 42, PHY block 44 and MAC block 46. The PHY circuit comprises a decimation filter and digital RX chain (DRX) for performing the demodulation function (not shown). The clock generation circuit block comprises single frequency phase locked loop (PLL) circuit 48 and clock frequency dividers 50, 52, 54.
In operation, the analog signal 62 (RX DATA IN) received from the RF receiver front end module (FEM) is typically an intermediate frequency (IF) or a zero IF (ZIF) signal. This IF signal is input to the ADC 42 and converted to digital samples using an 80 MHz divided clock 56. All the divided clocks are generated by dividing a high rate 480 MHz clock generated by the Phase Locked Loop circuit 48 using a reference clock signal FREF. The PHY circuit and MAC blocks are also fed the 80 MHz divided clock which is generated by the divided by six clock divider circuit 50. A divide by two clock divider functions to divide the 80 MHz clock to generate a 40 MHz clock 58 which is fed to the PHY and MAC blocks. A divide by four clock divider functions to divide the 480 MHz PLL output clock to generate a 120 MHz clock 60 which is fed to the MAC block.
The output of the ADC 42 is a digital signal 64 sampled at high rate which is input to the PHY circuit. The PHY circuit generates the RX data (i.e. bits), which is input to the MAC block 46 for subsequent processing. The PHY circuit performs the typical baseband processing functions such as down sampling using a decimation filter block to generate a decimated signal and demodulation for extracting the information bits out of the received signal. Note that the entire digital chain is fed with low rate clock signals 34 which are generated by dividing the high rate clock 68 generated by the PLL 48 using clock divider circuits 50, 52, 54.
Single frequency PLLs can be used not only in RX chains but in TX circuits as well. An example prior art digital transmitter (DTX) chain clock scheme circuit utilizing a single frequency PLL is shown in FIG. 4. The typical digital TX chain, generally referenced 130, comprise data path blocks and clock generation blocks. The data path comprises digital TX circuit 132 which comprises modulation blocks (not shown), an interpolation filter 134 and a digital to analog converter (DAC) 136. The clock generation circuit comprises a single frequency PLL 138 and frequency dividers 140.
In operation, the information bits 143 output of the MAC are input to the digital TX block 132, where they are processed and converted to a complex baseband or IF signal 145. This output signal is then interpolated in the interpolation filter 134 to a high rate signal 146 (i.e. sample stream) and inserted to the DAC 136 to generate the TX DATA OUT signal. This signal is then fed to the analog transmitter. The high rate clock 142 used by the DAC and interpolation filter is generated by a Phase Locked Loop circuit 138 using a reference clock signal FREF. The output of the PLL is used to feed the DAC and the interpolation filter. The low rate clock 144 is an integer division of the high rate clock 142 generated by the clock divider circuit block 140. The low rate clock feeds the digital TX circuit 132 and the interpolation filer 134.
A major problem, however, associated with prior art clock generation schemes such as that of FIGS. 2, 3 and 4 is their inflexibility regarding their clock generation circuits. In these prior art circuits, the entire digital chain (TX or RX) is fed with a single frequency and its integer divisions. This creates frequency spurs in fixed locations in the frequency band, i.e. the generation of harmonics from the clocks used in the digital chain circuits.
In the case of a multi-transceiver system, where several radios transmit and/or receive simultaneously in different or similar frequency bands, each radio can be either an aggressor, i.e. a radio that is interfering with other radios in the same system, or a victim, i.e. a radio that suffers degradation due to the operation of other radios. In such systems it is of great importance that various radios are able to coexist with one another. The problems and issues raised related to implementing coexistence among the radios eventually affects system functionality by degrading it.
In particular digital clocks, their divisions or harmonics, driving large digital circuits, within one receiver or transmitter can interfere with other receivers. The amount of isolation required in order to prevent de-sensitization in such a case can be impractical. For example, in a system with an FM receiver and a Bluetooth receiver transmitter, the FM receiver can have a sensitivity of a several micro-volts at receiver input (e.g., ˜−110 dBV). The signal to noise ratio require to process the FM signal can be about 20 dB. In the same system a concurrently operating Bluetooth receiver or transmitter can have a clock driving its logic at the FM reception frequency (˜100 MHz). The voltage of such digital clocks is usually about 1 volt (or 0 dBV). The isolation required in order not to impact the sensitivity of the FM receiver will therefore be 0 dBV−(−110 dBV)+20 dB+margin=130 dB+margin. If it is desired to obtain a small de-sense of about 0.5 dB, the margin should be 10 dB, yielding an intractable isolation of 140 dB. In addition, designing a system with such isolation between two points is a daunting task but many coupling paths between the aggressor and victim can exist making the task almost impossible.
A prior art graph illustrating FM sensitivity versus frequency channel with Bluetooth in active mode is shown in FIG. 5. The graph was generated by an example system comprising a Bluetooth radio and FM receiver. The graph illustrates the sensitivity of an FM receiver in the presence of a co-located Bluetooth receiver or transmitter. The X-axis represents the FM center frequency in MHz and the Y-axis represents the FM receiver sensitivity level in dBm. Desensitized frequency bands can be seen. The spikes marked as 12, 14, 16 highlight the degradation in the FM sensitivity (8-14 dB degradation) due to harmonics generated by the digital clocks in the Bluetooth receiver/transmitter circuitry. For example, spikes 12, 14 are caused by the 9th and 10th harmonic, respectively, of internal digital clocks. Turning off parts of the Bluetooth radio (i.e. IP) reveals exactly which clock caused the desensitization effect at a given frequency. Note that the degradation caused by the Bluetooth harmonics would typically be sufficient to prevent a user from successfully receiving a desired distant weak FM station. Please note that a de-sensitization of 10 dB represents a link budget loss reducing the effective system range (in open space) by a factor of 3.
A prior art approach to handling the coexistence issues described supra is to attempt to mitigate the impact of the aggressor radio on the victim radio on the victim side using well-known frequency spur cancellation techniques. A major disadvantage of this approach is that it typically only attenuates the spur and does not remove it completely. In addition, such techniques require additional development time that increases system cost, require significant chip area also increasing cost and result in additional power consumption.
Another prior art approach to handling coexistence issues is to design the physical layout in such a way that the impact of the aggressor on the victim will be attenuated. In other words, the aggressor and victim radios are physically and electrically separated as much as possible. The radios can be electrically separated by adding decoupling capacitors to attenuate the leakage caused by the frequency spurs. It is noted, however, that this technique is not always feasible as it requires a very careful physical layout, has a chip area penalty associated with it and any beneficial results can only be known after silicon is available.
It is thus desirable to have a coexistence mechanism that overcomes the disadvantage of the prior art techniques described supra. The coexistence mechanism should preferably be implementable as a simple, all digital implementation and be capable of enabling the simultaneous operation of multiple radios whether located on the same chip or within the same communications device. More specifically, the coexistence mechanism should provide substantially de-sense relaxation without any requirements on the analog component side.